Rotating Sprocket Wheel Generator Source Code
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;**********************************************************************
; sproket.asm
;
; Author: Matt Bennett
; Revision: 1.0
; Revision Date: February 11 1999
; Start Date: Jan 14 1999
;
; Rotaing sprocket wheel generator. Draws a rotating sprocket
; wheel on a analog X-Y oscilloscope.
;
; Generate 2 sine waves in quadrature, using a 128 entry lookup
; table and 2 6 bit R/2R resistor ladder D/A converters.
; Make the appearance of rotating sprocket teeth by keying
; a separate output according to another timer.
;**********************************************************************
;**********************************************************************
; compiler directives
;**********************************************************************
LIST p=16F84
#include "P16F84.INC"
__CONFIG _CP_OFF & _WDT_OFF & _HS_OSC & _PWRTE_ON
; code protect off, watchdog timer off,
; high speed oscillator, power up timer on
;**********************************************************************
; equates
;**********************************************************************
ramstart equ 0x0c
count equ ramstart + 0x00
delaycount equ ramstart + 0x01
schigh equ ramstart + 0x02
sclow equ ramstart + 0x03
sproket_count equ ramstart + 0x04
sproket_count_high equ ramstart + 0x05
temp equ ramstart + 0x06
;**********************************************************************
org 0x00
start
goto main
org 0x04
interrupt ; we should never get here
return
main
call initialize ; go set up
main_loop
movlw HIGH portalookup ;get the port a output value
movwf PCLATH
clrc
rrf count,w ; get every value twice
call portalookup
btfss sproket_count,0x04; check to see if wee need to
iorlw b'00010000' ; make a tooth
movwf PORTA
movlw HIGH portblookup; get the port b output value
movwf PCLATH
clrc
rrf count,w
call portblookup
nop ; to keep the timing somewhat even
nop
movwf PORTB
incf sproket_count,f
incf count,f
skpz
goto done_this_round_wait
movlw .16 ; add 16 to sprocket count high
addwf sproket_count_high,f
skpnc ; if carry,
incf sproket_count,f ; increment sprocket count
goto main_loop
done_this_round_wait
nop ; again to keep timing somewhat even
nop
nop
nop
done_this_round
goto main_loop
initialize
bsf STATUS,RP0 ; move to bank1
clrf INTCON ; clear the INTCON register
movlw b'10000100' ; for the OPTION register
; |---------------disable weak pullups
; |--------------int on falling edge of INT
; |-------------TMR0 from internal inst. clock
; |------------inc tmr0 on l->h from ext.
; |-----------prescaler assigned to tmr0
; |||--------prescaler 1:16
movwf OPTION_REG
movlw b'00000000' ; for the TRISA register
; set all to outputs
movwf TRISB
movlw b'00000000' ; for the TRISB register
; set all to output
movwf TRISA
bcf STATUS,RP0 ; back to page 0
clrf count
incf count,f
return
org 0x0200
portalookup ; lookup tables for port A part of sinewave
addwf PCL,f
retlw 07
retlw 08
retlw 08
retlw 09
retlw 09
retlw 09
retlw 0A
retlw 0A
retlw 0A
retlw 0B
retlw 0B
retlw 0B
retlw 0C
retlw 0C
retlw 0C
retlw 0D
retlw 0D
retlw 0D
retlw 0D
retlw 0E
retlw 0E
retlw 0E
retlw 0E
retlw 0E
retlw 0F
retlw 0F
retlw 0F
retlw 0F
retlw 0F
retlw 0F
retlw 0F
retlw 0F
retlw 0F
retlw 0F
retlw 0F
retlw 0F
retlw 0F
retlw 0F
retlw 0F
retlw 0F
retlw 0F
retlw 0E
retlw 0E
retlw 0E
retlw 0E
retlw 0E
retlw 0D
retlw 0D
retlw 0D
retlw 0D
retlw 0C
retlw 0C
retlw 0C
retlw 0B
retlw 0B
retlw 0B
retlw 0A
retlw 0A
retlw 0A
retlw 09
retlw 09
retlw 09
retlw 08
retlw 08
retlw 07
retlw 07
retlw 07
retlw 06
retlw 06
retlw 05
retlw 05
retlw 05
retlw 04
retlw 04
retlw 04
retlw 03
retlw 03
retlw 03
retlw 02
retlw 02
retlw 02
retlw 02
retlw 01
retlw 01
retlw 01
retlw 01
retlw 00
retlw 00
retlw 00
retlw 00
retlw 00
retlw 00
retlw 00
retlw 00
retlw 00
retlw 00
retlw 00
retlw 00
retlw 00
retlw 00
retlw 00
retlw 00
retlw 00
retlw 00
retlw 00
retlw 00
retlw 00
retlw 01
retlw 01
retlw 01
retlw 01
retlw 02
retlw 02
retlw 02
retlw 02
retlw 03
retlw 03
retlw 03
retlw 04
retlw 04
retlw 04
retlw 05
retlw 05
retlw 05
retlw 06
retlw 06
retlw 07
retlw 07
org 0x0300
portblookup ; lookup tables for port b part of sinewave
addwf PCL,f
retlw 0FF
retlw 07E
retlw 0BE
retlw 03E
retlw 07E
retlw 0FE
retlw 03D
retlw 0BD
retlw 0FC
retlw 03B
retlw 0BB
retlw 0FA
retlw 079
retlw 0B8
retlw 0F7
retlw 036
retlw 075
retlw 0B4
retlw 0F3
retlw 032
retlw 071
retlw 0AF
retlw 0EE
retlw 0EC
retlw 02B
retlw 06A
retlw 068
retlw 0A7
retlw 0A5
retlw 0A4
retlw 0A2
retlw 0A1
retlw 0DF
retlw 09D
retlw 09C
retlw 09A
retlw 099
retlw 097
retlw 056
retlw 054
retlw 013
retlw 0D2
retlw 0D0
retlw 08F
retlw 04D
retlw 00C
retlw 0CB
retlw 08A
retlw 049
retlw 008
retlw 0C7
retlw 086
retlw 045
retlw 0C4
retlw 083
retlw 003
retlw 0C2
retlw 081
retlw 001
retlw 0C0
retlw 040
retlw 000
retlw 080
retlw 040
retlw 0C0
retlw 040
retlw 000
retlw 080
retlw 040
retlw 0C0
retlw 081
retlw 001
retlw 0C2
retlw 083
retlw 003
retlw 0C4
retlw 045
retlw 006
retlw 0C7
retlw 088
retlw 049
retlw 00A
retlw 0CB
retlw 08C
retlw 04D
retlw 00F
retlw 0D0
retlw 0D2
retlw 093
retlw 054
retlw 056
retlw 017
retlw 019
retlw 01A
retlw 01C
retlw 01D
retlw 01F
retlw 021
retlw 022
retlw 024
retlw 025
retlw 027
retlw 068
retlw 06A
retlw 0AB
retlw 0EC
retlw 0EE
retlw 02F
retlw 071
retlw 0B2
retlw 0F3
retlw 034
retlw 075
retlw 0B6
retlw 0F7
retlw 038
retlw 079
retlw 0FA
retlw 03B
retlw 0BB
retlw 0FC
retlw 03D
retlw 0BD
retlw 0FE
retlw 07E
retlw 0BE
retlw 03E
retlw 07E
end
